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MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 1 description application main memory unit for note pc, mobile etc. features type name 133mhz mh16d64akqc-10 MH16D64AKQC-75 - utilizes industry standard 8m x 16 ddr synchronous drams in tsop package , industry standard eeprom(spd) in tssop package - vdd=vddq=2.5v0.2v - double data rate architecture; two data transfers per clock cycle - bidirectional, data strobe (dqs) is transmitted/received with data - differential clock inputs (clk and /clk) - data and data mask referenced to both edges of dqs - /cas latency- 2.0/2.5 (programmable) - burst length- 2/4/8 (programmable) - auto precharge / all bank precharge controlled by a10 - 4096 refresh cycles /64ms - auto refresh and self refresh - row address a0-11 / column address a0-8 - sstl_2 interface - module 2bank configration - burst type - sequential/interleave(programmable) - commands entered on each positive clk edge max. frequency 100mhz the mh16d64akqc is 16777216 - word x 64-bit double data rate(ddr) synchronous dram mounted module. this consists of 8 industry standard 8m x 16 ddr synchronous drams in tsop with sstl_2 interface which achieves very high speed data rate up to 133mhz. this socket-type memory module is suitable for main memory in computer systems and easy to interchange or add modules. clk access time [component level] + 0.75ns + 0.8ns (front) (back) 1 2 199 200 pcb outline
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 2 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 2 vref 85 88 3 vss 4 87 90 5 dq0 6 89 92 7 dq1 8 91 94 9 vdd 10 93 96 11 dqs0 12 95 98 13 dq2 14 97 100 15 vss 16 99 102 17 dq3 18 101 104 19 dq8 20 105 106 21 vdd 107 108 23 dq9 24 109 110 25 dqs1 26 111 112 27 vss 28 113 114 29 dq10 30 115 116 31 dq11 32 117 118 33 34 119 120 35 ck0 36 121 122 37 /ck0 38 123 126 39 vss 40 125 128 41 dq16 42 127 130 43 dq17 44 129 132 45 vdd 46 131 134 47 dqs2 48 133 136 49 dq18 50 135 138 51 vss 52 137 140 53 dq19 54 139 142 55 dq24 56 141 144 57 vdd 58 143 146 59 dq25 60 145 148 61 dqs3 62 147 150 63 vss 64 149 152 65 dq26 66 151 154 67 dq27 68 153 156 69 vdd 70 155 158 71 nc 72 157 160 73 nc 74 159 162 75 vss 76 161 164 77 nc 78 163 166 79 nc 80 165 168 81 vdd 82 167 83 nc 84 pin no. pin name 173 175 177 179 181 183 185 187 189 191 193 195 197 199 vss dq4 dq5 vdd dm0 dq6 vss dq7 dq12 dq13 dm1 vss dq14 dq15 vdd vdd vss vss dq20 dq21 vdd dm2 dq22 vss dq23 dq28 vdd dq29 dm3 vss dq30 dq31 nc nc vss nc nc vdd nc nc vss ck2 /ck2 vdd cke1 nc a12 a9 vss a7 a5 a3 a1 vdd a10/ap ba0 /we /s0 nc vss dq32 dq33 dqs4 dq34 vss dq35 dq40 vdd dq41 dqs5 vss dq42 dq43 vdd vss vss dq48 dq49 vdd nc vss vss vdd cke0 nc a11 a8 vss a6 a4 a2 a0 ba1 /ras /cas /s1 vss dq36 dq37 vdd dq38 vss dq39 dq44 vdd dq45 dm5 vss dq46 vdd /ck1 ck1 vss dq52 dq53 vdd dq50 dq51 dq56 vdd dq57 dqs7 vss dq58 vdd sda scl vddspd vddid pin configuration vdd 103 86 169 171 nc: no connect vdd vdd vdd vdd vdd dm4 dq47 dqs6 vss dq59 , 22 124 pin no. pin name 174 176 178 180 182 184 186 188 190 192 194 196 198 200 dq54 dq55 dq60 vdd dq61 dm7 vss dq62 vdd sa0 sa1 sa2 nc 170 172 dm6 vss dq63 vdd nc
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 3 block diagram /ck0 serial pd scl sda a0 a1 a2 vdd vss d0 - d7 d0 - d7 /s0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 cke0 d0 - d3 /ras d0 - d7 /cas d0 - d7 /we d0 - d7 ba0,ba1,a<11:0> d0 - d7 ck0 22 w i/o 0 i/o 1 i/o 2 i/o 3 /s d0 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 /s d1 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 /s d4 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 /s d5 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 /s1 4loads cke1 d4 - d7 u dm dqs1 u dqs dm1 l dm dqs0 l dqs dm0 u dm u dqs l dm l dqs /s l dm dqs4 l dqs dm4 l dm l dqs /s u dm dqs5 u dqs dm5 u dm u dqs l dm dqs2 l dqs dm2 l dm l dqs u dm dqs3 u dqs dm3 u dm u dqs /s /s /s l dm dqs6 l dqs dm6 l dm l dqs u dm dqs7 u dqs dm7 u dm u dqs vddspd spd vref d0 - d7 vddid sa0 sa1 sa2 wp /ck1 ck1 4loads /ck2 ck2 0 loads note: dq wiring may differ from that described in this drawing; however dq/dm/dqs relationships are maintained as shown. vdd id strap connections: (for memory device vdd, vddq) strap out (open): vdd=vddq strap in (closed): vdd=vddq
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 4 pin function ck0-2,/ck0-2 input clock: ck0-2 and /ck0-2 are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck0-2 and negative edge of /ck0-2. output (read) data is referenced to the crossings of ck0-2 and /ck0-2 (both directions of crossing). cke0-1 input clock enable: cke0-1 controls internal clock. when cke0-1 is low, internal clock for the following cycle is ceased. cke0-1 is also used to select auto / self refresh. after self refresh mode is started, cke0-1 becomes asynchronous input. self refresh is maintained as long as cke0-1 is low. /s0-1 input chip select : when /s0-1 is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-11. the column address is specified by a0-8. a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0-1 input dq 0-64 input / output dqs0-7 vdd, vss power supply power supply for the memory array and peripheral circuitry. bank address: ba0-1 specifies one of four banks in sdram to which a command is applied. ba0-1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. symbol type description input vref input sstl_2 reference voltage. vddspd power supply power supply for spd sda input / output this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected to vdd to act as a pullup. scl input / output this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl to vdd to act as a pullup. sa0-2 address pins used to select the serial presence detect. input dm0-7 input / output input data mask: dm is an input mask signal for write data. input data is masked when dm0-7 is sampled high along with that input data during a write access. dm0-7 is sampled on both edges of dqs0-7. although dm pins are input only, the dm0-7 loading matches the dq0-63 and dqs0-7 loading. vddid vdd identification flag out put
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 5 basic functions the mh16d64akqc provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /s0 chip select : l=select, h=deselect /ras command /cas command /we command cke0 refresh option @refresh command a10 precharge option @precharge or read/write command ck0 define basic commands activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke0 =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. /ck0
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 6 command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /s /ras /cas /we ba0,1 a10 /ap a0-9, 11 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h h l l h h v v v single bank precharge pre h h l l h l v l x precharge all banks prea h h l l h l h x column address entry & write write h h l h l l v l v column address entry & write with auto-precharge writea h h l h l l v h v column address entry & read read h h l h l h v l v column address entry & read with auto-precharge reada h h l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h h l h h l x x x mode register set mrs h h l l l l l l v x note 1 note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a11 provide the op-code to be written to the selected mode register. 2
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 7 function truth table current state /s /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop l l l h x refa auto-refresh l l l l op-code, mode-add mrs mode register set row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge l h l l ba, ca, a10 write writea l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 5 5 3 2 illegal
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 8 function truth table (continued) current state /s /ras /cas /we address command action write (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 3 3 2 2 2 2 2
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 9 function truth table (continued) current state /s /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea nop (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 2 2 2 2 2 2 2 2
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 10 function truth table (continued) current state /s /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. notes
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 11 current state cke0 n-1 cke0 n /s0 /ras /cas /we add action self- refresh h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) all banks idle h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle l h x x x x x exit clk suspend at next cycle l l x x x x x maintain clk suspend function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable ck0 and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. notes 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 12 simplified state diagram row active idle pre charge power down reada writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term write read
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 13 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or multifunctioning. 1. apply vdd before or the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable condition for 200us after stable power and clk, apply nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs 6. issue mrs for the mode register and to reset the dll 7. issue 2 or more auto refresh commands 8. maintain stable condition for 200 cycle after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks in discrete are in idle state. after tmrd from a mrs command, the ddr dimm is ready for new command. r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 r 2 4 8 r r r r r 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 dr 0 ltmode bt bl 0 0 0 /s0 /ras /cas /we a11-a0 /ck0 v ck0 ba0 ba1 cl latency mode /cas latency r r 2 r r r 2.5 r 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 dll reset no yes
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 14 extended mode register dll disable / enable mode can be programmed by setting the extended mode register (emrs). the extended mode register stores these data until the next emrs command, which may be issued when all banks in discrete are in idle state . after trsc from a emrs command, the ddr dimm is ready for new command. /s0 /ras /cas /we a11-a0 /ck0 v ck0 ba0 ba1 0 1 dll disable dll enable dll disable a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 0 0 dd 0 0 0 ds qfc 0 0 0 0 0 1 drive strength normal weak 0 1 qfc disable enable
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 15 /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 16 absolute maximum ratings dc operating conditions (ta=0 ~ 70 , unless otherwise noted) capacitance (ta=0 ~ 70 , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 3.7 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vss -0.5 ~ vdd+0.5 v io output current 50 ma pd power dissipation ta = 25 w topr operating temperature 0 ~ 70 tstg storage temperature -45 ~ 100 symbol parameter limits unit min. typ. max. vdd supply voltage 2.3 2.5 2.7 v vih(dc) high-level input voltage vref + 0.18 vdd+0.3 v vil(dc) low-level input voltage -0.3 vref - 0.18 v vref input reference voltage 0.49*vdd 0.51*vdd v 0.5*vdd vin(dc) input voltage level, ck0 and /ck0 -0.3 vdd + 0.3 v vid(dc) input differential voltage, ck0 and /ck0 0.36 vdd + 0.6 v vtt i/o termination voltage vref - 0.04 v vref + 0.04 notes 6 5 7 c c c symbol ci(a) ci(c) ci(k) ci/o parameter input capacitance, address pin input capacitance, control pin input capacitance, ck0 pin input capacitance, i/o pin test condition limits(max.) unit vi - 1.25v f=100mhz vi = 25mvrm 45 pf pf pf pf 45 30 20 c o c o 8 notes 11 11 11 11
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 17 average supply current from vdd (ta=0 ~ 70 , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70 , vdd = vddq = 2.5 0.2v, vss =vssq= 0v, unless otherwise noted) tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd -10 -75 active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck min ma ma ma self refresh current: cke 0.2v auto refresh current: t rc = t rfc (min) operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; iout = 0 ma active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs changing once per clock cycle idd2p precharge power-down standby current: all banks idle; power-down mode; cke vil (max); t ck = t ck min ma operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; iout= 0 ma;address and control inputs changing once per clock cycle operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle parameter/test conditions idd4r idd3n ma ma ma ma ma ma idd6 idd5 idd4w idd3p idd2n idd1 idd0 notes unit limits(max) symbol symbol parameter/test conditions limits min. max. unit vih(ac) vil(ac) vid(ac) vix(ac) high-level input voltage (ac) low -level input voltage (ac) input differential voltage, clk and /clk input crossing point voltage, clk and /clk vref + 0.35 vref - 0.35 v v v v 0.7 0.5*vdd-0.2 vdd + 0.6 ioz i i off-state output current /q floating vo=0~v dd q input current / vin=0 ~ vddq a a -10 -16 10 16 0.5*vdd +0.2 notes 7 8 9 c o c o
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 18 ac timing requirements (component level) (ta=0 ~ 70 , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) tck 1.1 0.9 1.1 0.9 read preamble trpre ns thp-1.0 thp- 0.75 output dqs valid window tqh ns +0.6 -0.6 +0.5 -0.5 dq valid data delay time from dqs tdqsq tclmin or tchmin tclmin or tchmin ns 15 10 15 10 cl=2 19 19 tck 0.55 0.45 0.55 0.45 clk low level width tcl clk cycle time tck cl=2.5 16 15 14 14 ac characteristics -10 -75 0.6 0.4 0.6 0.4 1.2 0.9 1.2 0.9 0.25 0.25 0.6 0.4 0.6 0.4 0 0 15 15 0.2 0.2 0.2 0.2 0.35 0.35 0.35 0.35 1.25 0.75 1.25 0.75 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 2 1.75 tck ns ns tck tck ns ns tck tck tck tck tck ns ns ns ns ns ns ns 0.6 0.5 0.6 0.5 15 8 15 7.5 tck 0.45 0.55 0.45 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 max. min. max. min. parameter 0.55 read postamble trpst twpre write preamble twpst write postamble twpres write preamble setup time input hold time (address and control) tih tis input setup time (address and control) tmrd mode register set command cycle time tdsh dqs falling edge hold time from clk tdss dqs falling edge to clk setup time tdqsl dqs input low level width tdqsh dqs input high level width tdqss write command to first dqs latching transition thp clock half period data-out-low impedance time from clk//clk tlz thz data-out-high impedance time from clk//clk tdipw dq and dm input pulse width (for each input) input hold time(dq,dm) input setup time (dq,dm) tds tdh tch clk high level width ns dq output valid data delay time from clk//clk tdqsck dq output valid data delay time from clk//clk ns tac notes unit symbol c o
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 19 18 17 15.6 15.6 1 1 1 1 200 200 80 75 1 1 15 15 15 15 20 20 20 20 80 75 70 65 120,000 50 120,000 45 u s tck tck tck ns tck ns ns ns ns ns average periodic refresh interval trefi exit power down to -read command txprd exit power down to command txpnr txsrd exit self ref. to -read command txsnr exit self ref. to non-read command twtr internal write to read command delay ns 35 35 auto precharge write recovery + precharge time tdal -10 -75 ac characteristics max. min. max. min. parameter twr write recovery time trrd act to act delay time row precharge time row to column delay trp trcd trfc auto ref. to active/auto ref. command period ns row cycle time(operation) trc row active time ns tras notes unit symbol output load condition (for component measurement) dq output timing measurement reference point v ref v ref dqs v ou v ref 30pf 50ohm v tt =v ref zo=50 ohm ac timing requirements(continues) (ta=0 ~ 70 , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) c o
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 20 notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +/-2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specification are tested after the device is properly initialized. 11. this parameter is sampled. vddq = +2.5v+/-0.2v, vdd = +2.5v+/-0.2v, f =100mhz, ta = 25 , vout(dc)= vddq/2, vout(peak to peak) = 25mv, dm inputs are grouped with i/o pins - reflecting the fact that they are matched in laoding (to faciliate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilized. exception: during the period before vref stabilizes, cke=< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and clk & /clk slew rate >1.0v/ns. c o
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 21 tac tdqsck tdqss /clk dqs tis tih vref clk valid data read operation tcl tch tck tdqsq tqh trpre trpst dqs /clk clk tds tdh twpre write operation / tdqss=max. tdss twpres twpst dqs /clk clk tdqss tds tdh twpre write operation / tdqss=min. tdsh twpres twpst dq dq dq cmd & add. (component level) tdqsl tdqsh tdqsl tdqsh
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 22 a precharge command can be issued at bl/2 from a read command without data loss. precharge all bank activation and precharge all (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa bl/2 operational description (component level) bank activate the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a11-0. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc,although the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. qa qa qa qa qa qa qa /clk clk
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 23 read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl-1) consecutive data when the burst length is bl. the start address is specified by a11,a8-a0, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge(reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2 after reada. the next act command can be issued after (bl/2+trp) from the previous reada. multi bank interleaving read (bl=8, cl=2) /clk command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length dqs qa clk qa qa qa qa qa qa qa qb qb qb qb qb qb qb qb
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 24 read with auto-precharge (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 1 00 act xb xb 00 internal precharge start trcd trp bl/2 + trp bl/2 dqs /clk clk qa qa qa qa qa qa qa qa read auto-precharge timing (bl=8) command act read internal precharge start timing dq cl=2.5 bl/2 dq cl=2 qa /clk clk qa qa qa qa qa qa qa qa qa qa qa qa qa qa qa
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 25 write after trcd from the bank activation, a write command can be issued. 1st input data is set from the write command with data strobe input, following (bl-1) data are written into ram, when the burst length is bl. the start address is specified by a11,a8-a0, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last data to the pre command, the write recovery time (twrp) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next act command can be issued after tdal from the last input data cycle. write with auto-precharge (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trcd da0 dqs /clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb multi bank interleaving write (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd trcd pre xa 0 00 pre dqs /clk clk da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 26 burst interruption [read interrupted by read] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1clk. [read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 read interrupted by read (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak qak qak qak qak qak qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 27 read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 28 [read interrupted by burst stop] burst read operation can be interrupted by a burst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by term (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 29 [read interrupted by write with term] read interrupted by term (bl=8) cl=2.5 command dq q0 q1 q2 q3 /clk clk read term dqs write d 0 d 1 d 2 d 3 d 4 d 5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 30 write interrupted by write (bl=8) command a0-9,11 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 [write interrupted by write] burst write operation can be interrupted by write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(twtr) is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". twtr is referenced from the first positive edge after the last data input. dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk write interrupted by read (bl=8, cl=2.5) command a0-9,11 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr /clk clk
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 31 [write interrupted by precharge] burst write operation can be interrupted by precharge of the same or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. command write interrupted by precharge (bl=8, cl=2.5) a0-9,11 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs dm twr /clk clk
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 32 [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-9,11 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 128mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-11 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk extended mode register set mode register set, reset dll
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 33 [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-11 ba0,1 txsnr self refresh exit /clk clk x y x y txsrd act read
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 34 [ asynchronous self refresh] asynchronous self -refresh mode is entered by cke=l within 2 tclk after issuing a refa command (/cs=/ras=/cas=l,/we=h). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. asynchronous self-refresh /ras cke /cs /cas /we a0-11 ba0,1 txsnr self refresh exit max 2 tclk /clk clk act
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 35 [power down] the purpose of clk suspend is power down. cke is synchronous input except during the self-refresh mode. a command at cycle is ignored. from cke=h to normal function, dll recovery time is not required in the condition of the stable clk operation during the power down mode. /clk clk power down by cke command pre cke command act cke standby power down active power down nop nop dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 [dm control] dm is defined as the data mask for writes. during writes,dm masks input data word by word. dm to write mask latency is 0. d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 /clk clk q0 q1 q6 valid nop nop valid txpnr/ txprd
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 36 outline unit.mm 20.00 31.75 4.00 6.00 0.25 max 2.55 4.00
MH16D64AKQC-75,-10 1,073,741,824 -bit (16,777,216-word by 64-bit) double data rate synchronous dram module mit-ds-0400-0.0 2 .nov.2000 preliminary spec. some contents are subject to change without notice. mitsubishi lsis mitsubishi electric 37 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor hom e page ( http://www.mitsubishichips.com ). 4.when using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 7.if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.

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